Tunneling Field-Effect Transistors: The Next-Generation Devices

A TFET has been considered as one of the most promising candidates for a next-generation electron device. It is because the SS of TFETs can be smaller than 60 mV/dec at room temperature, which is the physical limit of MOSFETs. Also, TFETs are immune to short channel effects thanks to their low Ioff. Especially, for the accurate evaluation and prediction of the electrical characteristics of TFETs, modeling study has become more important. However, because the operation principle of TFETs is totally different than that of MOSFETs, there is much room for improvement in TFET TCAD modeling. In this paper, some recent research results will be reviewed: hetero-gate-dielectric (HG) TFETs [1], scaling-down trend [2], ambipolar behavior, SS degradation, drain current saturation [3], analytical modeling [4], random dopant fluctuation and circuit applicability. HG TFETs: HG TFETs have been proposed for high performance and low-power consumption. Also, device design has been optimized by modulating Lhigh-k. By using a local minimum of Ec at the tunneling junction and placing silicon oxide whose relative permittivity is low at the drain side, the optimized HG TFETs showed improved device performance than conventional TFETs such as SiO2–only and high-k-only TFETs in terms of Ion, SS and Iamb. Scaling-Down Trend: Comparative study of tunneling FETs and MOSFETs has been performed in terms of SS, Ion/Ioff ratio, Ioff and Ion for low-power consumption. Tunneling FETs exhibit extremely small SS and off-current and good immunity to short channel effects compared with MOSFETs. Although the Ion of tunneling FETs is lower than that of MOSFETs, it is observed that lower bandgap substrate such as SSOI can boost the on current at the sacrifice of Ion/Ioff ratio due to rapid Ioff increase. It is expected that the tunneling FET can be a good alternative to the MOSFET for low-power application. Ambipolar Behavior: The effect of ambipolar behavior on TFETs has been evaluated by using ambipolarity factor ν. Because low-power consumption is one of the biggest advantages of TFETs, suppressing ambipolar current is as important as boosting on-current. The introduction of ν makes the analysis of ambipolarity easier. It has been confirmed that ambipolarity can be suppressed effectively by introducing novel device structures and optimizing tox, VDD, ND and NB. SS Degradation: The extraction method of RCH and RTUN has been proposed for TFETs. Based on the results, we classified the operation region of TFETs into two categories: the tunneling-dominant and drift-dominant region. In the tunneling-dominant region, because IDS is dominated by RTUN rather than RCH, the instantaneous SS increases with increasing VOV which is related to WTUN saturation. The reduction of RTUN makes tunneling-dominant TFETs drift-dominant. In the drift-dominant region, like MOSFETs, mobility engineering will be necessary for higher ION. Drain Current Saturation: The limiting mechanism of ID of TFETs has been investigated based on simulation results. It has been shown that the inversion layer formation results in ΨS pinning, which makes band-to-band tunneling current difficult to be modulated by the gate voltage. It has also been revealed that most of the inversion carriers of TFETs are provided through thermionic emission from the drain. Only negligible portion of the inversion carriers are supplied from the source through band-to-band tunneling. Thus, the formation of the inversion layer is determined by VGD rather than VGS. For quantitative analysis, Vinv has been extracted by using the relationship between CGD and VGS. The extracted Vinv values predict the inversion layer formation and ID saturation accurately. Analytical Modeling: An analytical model of single-gate SOI TFETs has been presented. The analytical model is based on two-dimensional Poisson’s equation. Calculated potential and electric field intensity are in excellent agreement with FEM results. From those results, transfer characteristics of TFETs have been calculated. Based on the results, we obtained the IDS-VGS characteristics numerically by using G. It has been shown that the proposed model can give an insight on the underlying physics of TFETs such as SCEs. Random Dopant Fluctuation: RDF effects of TFETs induced by source dopants are critical because the tunneling junction between source and body determines tunneling current of TFETs. It has been found that RDF effects become more severe as supply voltage decreases. Therefore, they should be suppressed so that TFETs meet the requirements of next-generation devices. Increasing the NS of TFETs is one of the design solutions. Circuit Applicability: The low-power applicability of HG TFETs has been discussed. Because HG TFETs show higher Ion and lower capacitance than SiO2and high-k-only TFETs, more aggressive voltage reduction is possible. It has been confirmed that HG TFETs is appropriate for low-power circuit design.